RISC-V/Paging

Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the satp CSR. This article will describe these steps.

Paging type can be determined at runtime using the device tree, its typically located in the CPU specific nodes, such as `cpu@x` where x denotes which number of CPU it is, it will be located under the `mmu-type` property in the form of a string such as `riscv,svY` is either "32", "39", "48", or "57" depending on paging type.

Terminology

There are many acronyms and other terms that are used in the RISC-V specification which, for the purpose of brevity and consistency, will be used in this article as well. I will assume a baseline knowledge of the purpose and basics of paging and virtual addressing.

PPNs and VPNs

A physical page number (or PPN) is a unique, page-aligned identifier for a page in physical memory. The number of PPN segments for an address will depend on the paging mode.

To construct a PPN from a physical address, you can simply (logically, not arithmetically) shift the value right by 12 bits (as 2**12 = 4096). Note that this operation will truncate the offset into the page, if the address was not page-aligned.

A virtual page number (or VPN) is very similar to a PPN, but in the virtual address space. Again, the number of VPN segments for a virtual address will depend on the paging mode.

RSW

Bits marked as RSW indicate that they can be written, read, and handled in any way the OS wants without causing issues. These can be used as OS-specific flags.

RISC-V Page Table Layout

There are various paging modes available in the RISC-V ISA, differing by the number of virtual address bits:

Name	Memory Size	SXLEN
Sv32	4GiB	32-bit only
Sv39	512GiB	64-bit only
Sv48	256TiB	64-bit only
Sv57	128PiB	64-bit only

Feel free to choose between these modes as you see fit; this page will describe all of them. Note that in 64-bit systems, Sv39 is more than enough for most hobby operating systems (though it is not much more difficult to go further).

Sv32

Sv32 is the only available paging mode for a 32 bit system, it provides 32 bit virtual addresses, and 34 bit physical addresses.

Address and PTE Layouts

Sv32 virtual address

Bit Range (inclusive)	Length (bits)	Description
0-11	12	Page offset
12-21	10	Page VPN (VPN[0])
22-31	10	Megapage VPN (VPN[0])

Sv32 physical address

Bit Range (inclusive)	Length (bits)	Description
0-11	12	Page offset
12-21	10	PPN[0]
22-33	12	PPN[1]

Sv32 page table entry layout

Bit Range (inclusive)	Length (bits)	Description
0	1	Valid flag (V)
1	1	Readable flag (R)
2	1	Writable flag (W)
3	1	Executable flag (X)
4	1	U-mode accessible flag (U)
5	1	Global flag (G)
6	1	Accessed flag (A)
7	1	Dirty flag (D)
8-9	2	RSW
10-19	10	PPN[0]
20-31	12	PPN[1]

Sv39

Sv39 is the simplest paging mode for 64-bit systems (though larger modes are not too much more difficult to implement). It supports the standard 4KiB pages, as well as 2MiB megapages and 1GiB gigapages.

TODO: actually describe what a page table looks like, and also PTE's RWX encoding

Address and PTE Layouts

Sv39 virtual address

Bit Range (inclusive)	Length (bits)	Description
0-11	12	Page offset
12-20	9	Page VPN (VPN[0])
21-29	9	Megapage VPN (VPN[1])
30-38	9	Gigapage VPN (VPN[2])

Sv39 physical address

Bit Range (inclusive)	Length (bits)	Description
0-11	12	Page offset
12-20	9	PPN[0]
21-29	9	PPN[1]
30-55	26	PPN[2]

Sv39 page table entry layout

Bit Range (inclusive)	Length (bits)	Description
0	1	Valid flag (V)
1	1	Readable flag (R)
2	1	Writable flag (W)
3	1	Executable flag (X)
4	1	U-mode accessible flag (U)
5	1	Global flag (G)
6	1	Accessed flag (A)
7	1	Dirty flag (D)
8-9	2	RSW
10-18	9	PPN[0]
19-27	9	PPN[1]
28-53	26	PPN[2]
54-60	7	Reserved
61-62	2	PBMT (TODO)
63	1	N bit (TODO)

Sv48

TODO: Explain

Address and PTE Layouts

Sv48 virtual address

Bit Range (inclusive)	Length (bits)	Description
0-11	12	Page offset
12-20	9	Page VPN (VPN[0])
21-29	9	Megapage VPN (VPN[1])
30-38	9	Gigapage VPN (VPN[2])
39-47	9	(VPN[3])

Sv48 physical address

Bit Range (inclusive)	Length (bits)	Description
0-11	12	Page offset
12-20	9	(PPN[0])
21-29	9	(PPN[1])
30-38	9	(PPN[2])
39-47	9	(PPN[3])

Sv48 page table entry layout

Bit Range (inclusive)	Length (bits)	Description
0	1	Valid flag (V)
1	1	Readable flag (R)
2	1	Writable flag (W)
3	1	Executable flag (X)
4	1	U-mode accessible flag (U)
5	1	Global flag (G)
6	1	Accessed flag (A)
7	1	Dirty flag (D)
8-9	2	RSW
10-18	9	PPN[0]
19-27	9	PPN[1]
28-36	9	PPN[2]
37-53	17	PPN[3]
54-60	7	Reserved
61-62	2	PBMT (TODO)
63	1	N bit (TODO)

Sv57

TODO

Enabling Paging

TODO: Explain better

Paging on RISC-V is split into 4 different modes, 32 bit, 39 bit, 48 bit, and 57 bit. 32 bit is only available on 32 bit systems, and not available on 64 bit systems. Paging is handled by the `SATP` CSR which contains 3 separate sections, the PPN(Physical Page Number) which is similar to the physical address, the ASID(Address Space Identifier), and finally, the Mode. To enable paging you need to write a paging mode into the Mode section of the `SATP` register. On 64 bits you can write 0 for no paging, 8 for Sv39, 9 for Sv48, 10 for Sv57, and in the future 11 will be available for 64 bits. On 32 bits you can write 0 for no paging, or 1 for Sv32.

Rust example code:

32 bits

pub unsafe fn enable_paging(root_page_table: usize) {
    let ppn = root_page_table >> 12;
    let mode = 1 << 31;

    let write = mode | ppn;

    core::arch::asm(
        "csrw satp, {}",
        in(reg) write
    );
}

64 bits

pub unsafe fn enable_paging(root_page_table: usize, mode: u8) {
    let ppn = root_page_table >> 12;
    let new_mode = (mode & 0xf) << 60;

    let write = mode | ppn;

    core::arch::asm(
        "csrw satp, {}",
        in(reg) write
    );
}