User contributions for Veloya
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1 September 2023
- 00:4800:48, 1 September 2023 diff hist +2,996 N Limine-zig Added basic info on code for getting x86 limine with zig working current Tag: Visual edit
31 August 2023
- 23:4523:45, 31 August 2023 diff hist +4 N Category:X86 Created the page, time to work on it
- 23:3423:34, 31 August 2023 diff hist +1,104 RISC-V/Paging Added information on Sv32, also added a section for RSW bits. Tag: Visual edit
16 February 2023
- 03:1503:15, 16 February 2023 diff hist +516 N CLINT VERY basic description of it, as well as a memory map as specified by the following link, update HIGHLY recommended https://sifive.cdn.prismic.io/sifive/ad5577a0-9a00-45c9-a5d0-424a3d586060_u74_core_complex_manual_21G3.pdf current Tag: Visual edit
10 February 2023
- 23:1823:18, 10 February 2023 diff hist +1,285 RISC-V/Paging Added paging enabling code, and a short explanation on it
- 18:1118:11, 10 February 2023 diff hist +1 m RISC-V/Paging Messed up on the bit sizes for PPN3 in Sv48
- 16:3816:38, 10 February 2023 diff hist +1,434 RISC-V/Paging Added some info about Sv48 paging
- 16:2116:21, 10 February 2023 diff hist +329 RISC-V/Paging Added a short explanation for getting the MMU type with the DT Tag: Visual edit
8 February 2023
- 14:2314:23, 8 February 2023 diff hist +1,134 N Interrupts Not a very good explanation, but I thought it'd be good enough, for now. current
- 02:5302:53, 8 February 2023 diff hist +1,190 PLIC Updated priorities and threshold section, I suggest someone double check just in case current
6 February 2023
- 13:5513:55, 6 February 2023 diff hist +840 PLIC Did my best to explain and demonstrate Claim/Complete Mechanism, I suggest someone who is more qualified review this later