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3 November 2023

  • 00:1100:11, 3 November 2023 diff hist +1 Category:RiverNo edit summary current
  • 00:1100:11, 3 November 2023 diff hist +85 N Category:RiverCreated page with "<span style="display:none">{{DISPLAYNAME:Category:river}}</span> See river."
  • 00:1000:10, 3 November 2023 diff hist +821 N RiverCreated page with "<span display="none">{{DISPLAYTITLE:river}}</span> Category:River River is an experimental capability-based operating system written by ThePuzzlemaker in Rust for RISCV64. (For those wondering, the name is taken from RISC-V: "RIscV" + "ER"). This project is not intended to be used in production, but instead just as a project for learning about advanced OS concepts and existing kernels. River takes inspiration from repnop's Vanadinite, the se..." current

2 November 2023

24 November 2022

23 November 2022

  • 21:2121:21, 23 November 2022 diff hist +891 N RISC-V/PagingCreated page with "Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the <code>satp</code> CSR. This article will describe these steps. == RISC-V Page Table Layout == There are various paging strategies available in the RISC-V ISA, differing by the number of virtual address bits: {| class="wikitable" |- ! Name !! Memory Size !! SXLEN |- | Sv32 || 4GiB || 32-bit only |- | Sv39 || 512GiB || 64-bit only |- |..."
  • 20:1120:11, 23 November 2022 diff hist −278 Main PageCreate a better welcome page Tag: Visual edit: Switched