RISC-V/Paging: Revision history

2 November 2023

• curprev 23:4223:42, 2 November 2023‎ ThePuzzlemaker talk contribs‎ 7,533 bytes −1‎ Fix category reference
• curprev 23:4223:42, 2 November 2023‎ ThePuzzlemaker talk contribs‎ 7,534 bytes +20‎ Add to Category:RISC-V

31 August 2023

• curprev 23:3423:34, 31 August 2023‎ Veloya talk contribs‎ 7,514 bytes +1,104‎ Added information on Sv32, also added a section for RSW bits. Tag: Visual edit

10 February 2023

• curprev 23:1823:18, 10 February 2023‎ Veloya talk contribs‎ 6,410 bytes +1,285‎ Added paging enabling code, and a short explanation on it
• curprev 18:1118:11, 10 February 2023‎ Veloya talk contribs‎ m 5,125 bytes +1‎ Messed up on the bit sizes for PPN3 in Sv48
• curprev 16:3816:38, 10 February 2023‎ Veloya talk contribs‎ 5,124 bytes +1,434‎ Added some info about Sv48 paging
• curprev 16:2116:21, 10 February 2023‎ Veloya talk contribs‎ 3,690 bytes +329‎ Added a short explanation for getting the MMU type with the DT Tag: Visual edit

24 November 2022

• curprev 03:1103:11, 24 November 2022‎ ThePuzzlemaker talk contribs‎ 3,361 bytes +1,570‎ No edit summary
• curprev 02:5302:53, 24 November 2022‎ ThePuzzlemaker talk contribs‎ 1,791 bytes +900‎ Describe PPNs and VPNs

23 November 2022

• curprev 21:2121:21, 23 November 2022‎ ThePuzzlemaker talk contribs‎ 891 bytes +891‎ Created page with "Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the <code>satp</code> CSR. This article will describe these steps. == RISC-V Page Table Layout == There are various paging strategies available in the RISC-V ISA, differing by the number of virtual address bits: {| class="wikitable" |- ! Name !! Memory Size !! SXLEN |- | Sv32 || 4GiB || 32-bit only |- | Sv39 || 512GiB || 64-bit only |- |..."