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Combined display of all available logs of FriendOS Wiki. You can narrow down the view by selecting a log type, the username (case-sensitive), or the affected page (also case-sensitive).
- 00:11, 3 November 2023 ThePuzzlemaker talk contribs created page Category:River (Created page with "<span style="display:none">{{DISPLAYNAME:Category:river}}</span> See river.")
- 00:10, 3 November 2023 ThePuzzlemaker talk contribs created page River (Created page with "<span display="none">{{DISPLAYTITLE:river}}</span> Category:River River is an experimental capability-based operating system written by ThePuzzlemaker in Rust for RISCV64. (For those wondering, the name is taken from RISC-V: "RIscV" + "ER"). This project is not intended to be used in production, but instead just as a project for learning about advanced OS concepts and existing kernels. River takes inspiration from repnop's Vanadinite, the se...")
- 23:49, 2 November 2023 ThePuzzlemaker talk contribs created page Template:Lowercase title (Created page with "<span style="display:none">{{DISPLAYTITLE:{{#if:{{NAMESPACE}}|{{NAMESPACE}}:|}}{{lcfirst:{{PAGENAME}}}}}}</span><noinclude> {{documentation|content= ==Purpose== This template makes the first letter in a page's title appear lowercase (MediaWiki otherwise forces titles to start with an uppercase letter). ==Usage== Just include it in the article: <nowiki>{{lowercase title}}</nowiki> ==Dependencies== This Template requires the Extension:ParserFunctions to work. }} <...")
- 23:45, 2 November 2023 ThePuzzlemaker talk contribs created page Category:Architectures (Created blank page)
- 23:42, 2 November 2023 ThePuzzlemaker talk contribs created page Category:RISCV (Created page with "TODO")
- 21:21, 23 November 2022 ThePuzzlemaker talk contribs created page RISC-V/Paging (Created page with "Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the <code>satp</code> CSR. This article will describe these steps. == RISC-V Page Table Layout == There are various paging strategies available in the RISC-V ISA, differing by the number of virtual address bits: {| class="wikitable" |- ! Name !! Memory Size !! SXLEN |- | Sv32 || 4GiB || 32-bit only |- | Sv39 || 512GiB || 64-bit only |- |...")
- 00:19, 23 November 2022 User account ThePuzzlemaker talk contribs was created