RISC-V/Paging
Revision as of 21:21, 23 November 2022 by ThePuzzlemaker (talk | contribs) (Created page with "Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the <code>satp</code> CSR. This article will describe these steps. == RISC-V Page Table Layout == There are various paging strategies available in the RISC-V ISA, differing by the number of virtual address bits: {| class="wikitable" |- ! Name !! Memory Size !! SXLEN |- | Sv32 || 4GiB || 32-bit only |- | Sv39 || 512GiB || 64-bit only |- |...")
Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the satp CSR. This article will describe these steps.
RISC-V Page Table Layout
There are various paging strategies available in the RISC-V ISA, differing by the number of virtual address bits:
| Name | Memory Size | SXLEN |
|---|---|---|
| Sv32 | 4GiB | 32-bit only |
| Sv39 | 512GiB | 64-bit only |
| Sv48 | 256TiB | 64-bit only |
| Sv57 | 128PiB | 64-bit only |
Feel free to choose between these strategies as you see fit; this page will describe all of them. Note that in 64-bit systems, Sv39 is more than enough for most hobby operating systems (though it is not much more difficult to go further).
Sv32
TODO
Sv39
TODO
Sv48
TODO
Sv57
TODO
Enabling Paging
TODO