Intel 64 Architecture

Architecture

The Intel 64 Architecture is a 64-bit extension of the 32-bit x86 IA-32 architecture. It was introduced around 2004, reimplementing AMD64, AMD's 64-bit extension.

Both AMD64 and Intel 64 Architecture (from henceforth referred to as I64A; Do not confuse with Itanium, referred to as IA64.) are collectively referred to as x86_64, and commonly as x64, or 64bit x86.

I64A introduces a new x86 Operating Mode to the existing set already present in IA-32 referred to as IA-32e, which has two sub-modes, IA-32e Compatibility Mode and IA-32e 64bit Mode.

Summary

I64A is the most common x86 architecture in use today, and as such, we will detail things present in I64A that are also present in other x86 architectures. We will describe average somewhat modern Intel CPU here.

When the system boots up, the Intel Managemenet Engine (IME) initializes the chipset, then loads the Motherboard Firmware from its ROM, and jumps to it. The Motherboard Firmware then initializes the computer, POSTs, and executes its defined Firmware Interface to load a Bootloader.

The two main Firmware Interfaces are BIOS and UEFI. BIOS is older, back from DOS days. UEFI is newer, and the current preferred standard for most non-legacy applications.

I64A has several operating modes.

• Protected Mode (native)
• Real-address Mode (emulated)
• System-management Mode (SMM)
• Compatibility Mode (IA-32e)
• 64-bit Mode (IA-32e)

Protected Mode

Main article: Protected Mode 32-bit GPR set. Instructions default to 32bit (operand size and address size). Addresses consist of a 16-bit Segment Selector and 32-bit offset.

Protected Mode (henceforth referred to as PM) supports both Paging and Segmentation. Segmentation is mandatory, though it can be configured to be essentially a no-op, a so-called Flat Segmentation Model, eg. if you want to use Paging only.

Segmentation is configured though a Global Descriptor Table.

Real-address Mode

Main article: Real-address Mode 16-bit GPR set. Essentially just emulates an 8086. Thus, 16-bit addresses with 4-bit Segment Registers for Segment Selection. Do note that Segment Registers are different from but interconnected with Segmentation! Segment Selection allows for the existence of several separate address spaces only, it is not a form of protected memory like PM's Segmentation - you cannot configure memory protection (which Protected Mode gets its name from) controls.

System-management Mode

Main article: System-management Mode It's a part of the APIs the Motherboard Firmware implementation uses for implementing certain features. Namely, the CPU switches to this mode when it receives a System Management Interrupt, that is, a certain Hardware Interrupt on the SMI line (which is kind of like the NMI line).

Not to be confused with the System Management Module. Thanks Intel.

64-bit Mode

In 64-bit mode, segmentation is mostly disabled. The segment registers still need to hold a valid Segment Selector for a valid Segment Entry, but the base field is not used in address calculations. Do note that there are GSBASE and FSBASE MSRs present which _are_ used in Effective Address calculations if the instruction has a FS or GS Segment Override Instruction Prefix. Those MSRs are written to with the base of the selected segment when their respective segment registers are written to (TODO verify, manual doesn't state as such)