RISC-V/Paging - Revision history

ThePuzzlemaker: Fix category reference

2023-11-02T23:42:30Z

Fix category reference

← Older revision		Revision as of 23:42, 2 November 2023
Line 1:		Line 1:
	[[Category:~~RISC-V~~]]		[[Category:RISCV]]
	Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp \| <code>satp</code> CSR]]. This article will describe these steps.		Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp \| <code>satp</code> CSR]]. This article will describe these steps.

ThePuzzlemaker: Add to Category:RISC-V

2023-11-02T23:42:06Z

Add to Category:RISC-V

← Older revision		Revision as of 23:42, 2 November 2023
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			[[Category:RISC-V]]
	Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp \| <code>satp</code> CSR]]. This article will describe these steps.		Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp \| <code>satp</code> CSR]]. This article will describe these steps.

Veloya: Added information on Sv32, also added a section for RSW bits.

2023-08-31T23:34:34Z

Added information on Sv32, also added a section for RSW bits.

@@ Line 15: / Line 15: @@
 A virtual page number (or VPN) is very similar to a PPN, but in the virtual address space. Again, the number of VPN segments for a virtual address will depend on the paging mode.
 == RISC-V Page Table Layout ==
@@ Line 36: / Line 39: @@
 === Sv32 ===
-TODO
+Sv32 is the only available paging mode for a 32 bit system, it provides 32 bit virtual addresses, and 34 bit physical addresses.
 === Sv39 ===
@@ Line 95: / Line 186: @@
 | 7 || 1 || Dirty flag (D)
 |-
-| 8-9 || 2 || RSW (TODO)
+| 8-9 || 2 || RSW
 |-
 | 10-18 || 9 || <nowiki>PPN[0]</nowiki>
@@ Line 169: / Line 260: @@
 | 7 || 1 || Dirty flag (D)
 |-
-| 8-9 || 2 || RSW (TODO)
+| 8-9 || 2 || RSW
 |-
 | 10-18 || 9 || <nowiki>PPN[0]</nowiki>

Veloya: Added paging enabling code, and a short explanation on it

2023-02-10T23:18:03Z

Added paging enabling code, and a short explanation on it

← Older revision		Revision as of 23:18, 10 February 2023
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	== Enabling Paging ==		== Enabling Paging ==

	TODO		TODO: Explain better

			Paging on RISC-V is split into 4 different modes, 32 bit, 39 bit, 48 bit, and 57 bit. 32 bit is only available on 32 bit systems, and not available on 64 bit systems.
			Paging is handled by the `SATP` CSR which contains 3 separate sections, the PPN(Physical Page Number) which is similar to the physical address, the ASID(Address Space Identifier), and finally, the Mode. To enable paging you need to write a paging mode into the Mode section of the `SATP` register. On 64 bits you can write 0 for no paging, 8 for Sv39, 9 for Sv48, 10 for Sv57, and in the future 11 will be available for 64 bits. On 32 bits you can write 0 for no paging, or 1 for Sv32.

			Rust example code:

			32 bits
			<syntaxhighlight lang="rust" line>
			pub unsafe fn enable_paging(root_page_table: usize) {
			let ppn = root_page_table >> 12;
			let mode = 1 << 31;

			let write = mode \| ppn;

			core::arch::asm(
			"csrw satp, {}",
			in(reg) write
			);
			}
			</syntaxhighlight>

			64 bits
			<syntaxhighlight lang="rust" line>
			pub unsafe fn enable_paging(root_page_table: usize, mode: u8) {
			let ppn = root_page_table >> 12;
			let new_mode = (mode & 0xf) << 60;

			let write = mode \| ppn;

			core::arch::asm(
			"csrw satp, {}",
			in(reg) write
			);
			}
			</syntaxhighlight>

Veloya: Messed up on the bit sizes for PPN3 in Sv48

2023-02-10T18:11:13Z

Messed up on the bit sizes for PPN3 in Sv48

← Older revision		Revision as of 18:11, 10 February 2023
Line 177:		Line 177:
	\| 28-36 \|\| 9 \|\| <nowiki>PPN[2]</nowiki>		\| 28-36 \|\| 9 \|\| <nowiki>PPN[2]</nowiki>
	\|-		\|-
	\| 37-53 \|\| 9 \|\| <nowiki>PPN[3]</nowiki>		\| 37-53 \|\| 17 \|\| <nowiki>PPN[3]</nowiki>
	\|-		\|-
	\| 54-60 \|\| 7 \|\| Reserved		\| 54-60 \|\| 7 \|\| Reserved

Veloya: Added some info about Sv48 paging

2023-02-10T16:38:14Z

Added some info about Sv48 paging

@@ Line 112: / Line 112: @@
 === Sv48 ===
-TODO
+TODO: Explain
 === Sv57 ===

Veloya: Added a short explanation for getting the MMU type with the DT

2023-02-10T16:21:24Z

Added a short explanation for getting the MMU type with the DT

← Older revision		Revision as of 16:21, 10 February 2023
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	Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp \| <code>satp</code> CSR]]. This article will describe these steps.		Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp \| <code>satp</code> CSR]]. This article will describe these steps.


			Paging type can be determined at runtime using the device tree, its typically located in the CPU specific nodes, such as `cpu@x` where x denotes which number of CPU it is, it will be located under the `mmu-type` property in the form of a string such as `riscv,svY` is either "32", "39", "48", or "57" depending on paging type.

	== Terminology ==		== Terminology ==

ThePuzzlemaker at 03:11, 24 November 2022

2022-11-24T03:11:35Z

@@ Line 37: / Line 37: @@
 === Sv39 ===
-TODO
+Sv39 is the simplest paging mode for 64-bit systems (though larger modes are not too much more difficult to implement). It supports the standard 4KiB pages, as well as 2MiB megapages and 1GiB gigapages.
 === Sv48 ===

ThePuzzlemaker: Describe PPNs and VPNs

2022-11-24T02:53:52Z

Describe PPNs and VPNs

← Older revision		Revision as of 02:53, 24 November 2022
Line 1:		Line 1:
	Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp \| <code>satp</code> CSR]]. This article will describe these steps.		Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp \| <code>satp</code> CSR]]. This article will describe these steps.

			== Terminology ==

			There are many acronyms and other terms that are used in the RISC-V specification which, for the purpose of brevity and consistency, will be used in this article as well. I will assume a baseline knowledge of the purpose and basics of paging and virtual addressing.

			=== PPNs and VPNs ===

			A physical page number (or PPN) is a unique, page-aligned identifier for a page in physical memory. The number of PPN segments for an address will depend on the paging mode.

			To construct a PPN from a physical address, you can simply (logically, not arithmetically) shift the value right by 12 bits (as 2**12 = 4096). Note that this operation will truncate the offset into the page, if the address was not page-aligned.

			A virtual page number (or VPN) is very similar to a PPN, but in the virtual address space. Again, the number of VPN segments for a virtual address will depend on the paging mode.

	== RISC-V Page Table Layout ==		== RISC-V Page Table Layout ==

	There are various paging ~~strategies~~ available in the RISC-V ISA, differing by the number of virtual address bits:		There are various paging modes available in the RISC-V ISA, differing by the number of virtual address bits:
	{\| class="wikitable"		{\| class="wikitable"
	\|-		\|-
Line 17:		Line 29:
	\|}		\|}

	Feel free to choose between these ~~strategies~~ as you see fit; this page will describe all of them. Note that in 64-bit systems, Sv39 is more than enough for most hobby operating systems (though it is not much more difficult to go further).		Feel free to choose between these modes as you see fit; this page will describe all of them. Note that in 64-bit systems, Sv39 is more than enough for most hobby operating systems (though it is not much more difficult to go further).

	=== Sv32 ===		=== Sv32 ===

ThePuzzlemaker: Created page with "Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the `satp` CSR. This article will describe these steps. == RISC-V Page Table Layout == There are various paging strategies available in the RISC-V ISA, differing by the number of virtual address bits: {| class="wikitable" |- ! Name !! Memory Size !! SXLEN |- | Sv32 || 4GiB || 32-bit only |- | Sv39 || 512GiB || 64-bit only |- |..."

2022-11-23T21:21:10Z

Created page with "Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the <code>satp</code> CSR. This article will describe these steps. == RISC-V Page Table Layout == There are various paging strategies available in the RISC-V ISA, differing by the number of virtual address bits: {| class="wikitable" |- ! Name !! Memory Size !! SXLEN |- | Sv32 || 4GiB || 32-bit only |- | Sv39 || 512GiB || 64-bit only |- |..."

New page

Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp | <code>satp</code> CSR]]. This article will describe these steps.

== RISC-V Page Table Layout ==

There are various paging strategies available in the RISC-V ISA, differing by the number of virtual address bits:
{| class="wikitable"
|-
! Name !! Memory Size !! SXLEN
|-
| Sv32 || 4GiB || 32-bit only
|-
| Sv39 || 512GiB || 64-bit only
|-
| Sv48 || 256TiB || 64-bit only
|-
| Sv57 || 128PiB || 64-bit only
|}

Feel free to choose between these strategies as you see fit; this page will describe all of them. Note that in 64-bit systems, Sv39 is more than enough for most hobby operating systems (though it is not much more difficult to go further).

=== Sv32 ===

TODO

=== Sv39 ===

TODO

=== Sv48 ===

TODO

=== Sv57 ===

TODO

== Enabling Paging ==

TODO