View source for IA32 Manual Conventions

Bit number 0 is the first, [[Least Significant Bit]].
Bit ranges are written inclusive. Example with [[Segment Selector|Segment Selectors]]:

[[File:Segment_Selectors_Screenshot_01.png|800px]]

Bit 0 is the least significant bit, bit 15 is the [[Most Significant Bit]]. Range "bits 3 through 15" ''include'' bit 3 and bit 15 and are 13 bits long, with bit 0 through 1 aka bit 0 and 1 being the [[Requested Priviledge Level|RPL]] and bit 2 (3rd bit) being the [[Table Indicator|TI]].
Additionally, in memory, this is stored [[Little Endian]], so the least significant half of the index + 3 bits for the flags is in the first byte and the most significant half of the index is in the second byte. 
Do note that eg. [[NASM]] treats <code>0b</code> as numeric literals, so it'll swap the bytes around - Thus, 
<pre>
mov ax, 0000_0000_0000_1000b
mov cs, ax
</pre>
Puts [[Segment Selector]] with [[Requested Priviledge Level|RPL]]=0 into the ''second'' (2, 0b10, 0x2) entry of the ''[[Global Descriptor Table|GDT]]'', with the 1 being the 4th bit aka bit 3 into the [[Code Segment Register|CS register]].
[[Category:X86]]