FriendOS Wiki - User contributions [en]

Category:River

2023-11-03T00:11:20Z

ThePuzzlemaker:

{{DISPLAYTITLE:Category:river}}
See [[River|river]].

Category:River

2023-11-03T00:11:06Z

ThePuzzlemaker: Created page with "{{DISPLAYNAME:Category:river}} See river."

{{DISPLAYNAME:Category:river}}
See [[River|river]].

River

2023-11-03T00:10:25Z

ThePuzzlemaker: Created page with "{{DISPLAYTITLE:river}} Category:River River is an experimental capability-based operating system written by ThePuzzlemaker in Rust for RISCV64. (For those wondering, the name is taken from RISC-V: "RIscV" + "ER"). This project is not intended to be used in production, but instead just as a project for learning about advanced OS concepts and existing kernels. River takes inspiration from repnop's Vanadinite, the se..."

{{DISPLAYTITLE:river}}
[[Category:River]]

River is an experimental capability-based operating system written by [[User:ThePuzzlemaker|ThePuzzlemaker]] in Rust for RISCV64. (For those wondering, the name is taken from RISC-V: "RIscV" + "ER"). This project is not intended to be used in production, but instead just as a project for learning about advanced OS concepts and existing kernels.

River takes inspiration from repnop's Vanadinite, the seL4 project, GWU Composite (which has some very helpful accompanying lectures), Fucshia/Zircon, and XV6/RISC-V. Thanks goes to all the amazing people who have helped me through my insanity as I try to figure this stuff out.

== Links ==

* GitHub: [https://github.com/ThePuzzlemaker/river ThePuzzlemaker/river]
* [[:Category:River|Category Index]]

Category:X86

2023-11-02T23:50:39Z

ThePuzzlemaker:

{{DISPLAYTITLE:Category:x86}}
[[Category:Architectures]]
TODO

Template:Lowercase title

2023-11-02T23:49:49Z

ThePuzzlemaker:

{{DISPLAYTITLE:{{#if:{{NAMESPACE}}|{{NAMESPACE}}:|}}{{lcfirst:{{PAGENAME}}}}}}

Template:Lowercase title

2023-11-02T23:49:26Z

ThePuzzlemaker: Created page with "{{DISPLAYTITLE:{{#if:{{NAMESPACE}}|{{NAMESPACE}}:|}}{{lcfirst:{{PAGENAME}}}}}}<noinclude> {{documentation|content= ==Purpose== This template makes the first letter in a page's title appear lowercase (MediaWiki otherwise forces titles to start with an uppercase letter). ==Usage== Just include it in the article: <nowiki>{{lowercase title}}</nowiki> ==Dependencies== This Template requires the Extension:ParserFunctions to work. }} <..."

{{DISPLAYTITLE:{{#if:{{NAMESPACE}}|{{NAMESPACE}}:|}}{{lcfirst:{{PAGENAME}}}}}}<noinclude>
{{documentation|content=

==Purpose==
This template makes the first letter in a page's title appear lowercase (MediaWiki otherwise forces titles to start with an uppercase letter).

==Usage==
Just include it in the article:
<nowiki>{{lowercase title}}</nowiki>

==Dependencies==
This Template requires the [[Extension:ParserFunctions]] to work.

}}
</noinclude>

Category:Architectures

2023-11-02T23:45:43Z

ThePuzzlemaker: Created blank page

Main Page

2023-11-02T23:45:14Z

ThePuzzlemaker: /* Helpful Links */ Make that actually link

== Welcome to the FriendOS Wiki! ==

The FriendOS Wiki is a community-driven wiki for the [https://discord.gg/U9feA9z669 FriendOS Discord server]. This wiki, as well as the Discord server, are intended to create a more inclusive, supportive, and welcoming environment for people learning about operating systems development, which historically is not very common. The purpose of this wiki is to provide resources for newbies and veterans alike, as well as allowing contributions from the community members so that people can easily create & share information about the concepts that they frequently work with. If you think you have something to contribute, make an account and start writing! If you have comments or questions, you can discuss the wiki in the #wiki channel on the Discord server.

== Helpful Links ==

* [https://discord.gg/U9feA9z669 Discord invite link]
* [[Special:AllPages|See all pages]]
* [[:Category:Architectures|Architectures Index]]

Main Page

2023-11-02T23:44:28Z

ThePuzzlemaker: /* Helpful Links */ Architectures index

Category:X86

2023-11-02T23:43:45Z

ThePuzzlemaker:

[[Category:Architectures]]
TODO

Category:RISCV

2023-11-02T23:43:30Z

ThePuzzlemaker:

[[Category:Architectures]]
TODO

Category:RISCV

2023-11-02T23:42:56Z

ThePuzzlemaker: Created page with "TODO"

TODO

RISC-V/Paging

2023-11-02T23:42:30Z

ThePuzzlemaker: Fix category reference

[[Category:RISCV]]
Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp | <code>satp</code> CSR]]. This article will describe these steps.

Paging type can be determined at runtime using the device tree, its typically located in the CPU specific nodes, such as `cpu@x` where x denotes which number of CPU it is, it will be located under the `mmu-type` property in the form of a string such as `riscv,svY` is either "32", "39", "48", or "57" depending on paging type.

== Terminology ==

There are many acronyms and other terms that are used in the RISC-V specification which, for the purpose of brevity and consistency, will be used in this article as well. I will assume a baseline knowledge of the purpose and basics of paging and virtual addressing.

=== PPNs and VPNs ===

A physical page number (or PPN) is a unique, page-aligned identifier for a page in physical memory. The number of PPN segments for an address will depend on the paging mode.

To construct a PPN from a physical address, you can simply (logically, not arithmetically) shift the value right by 12 bits (as 2**12 = 4096). Note that this operation will truncate the offset into the page, if the address was not page-aligned.

A virtual page number (or VPN) is very similar to a PPN, but in the virtual address space. Again, the number of VPN segments for a virtual address will depend on the paging mode.

=== RSW ===
Bits marked as RSW indicate that they can be written, read, and handled in any way the OS wants without causing issues. These can be used as OS-specific flags.

== RISC-V Page Table Layout ==

There are various paging modes available in the RISC-V ISA, differing by the number of virtual address bits:
{| class="wikitable"
|-
! Name !! Memory Size !! SXLEN
|-
| Sv32 || 4GiB || 32-bit only
|-
| Sv39 || 512GiB || 64-bit only
|-
| Sv48 || 256TiB || 64-bit only
|-
| Sv57 || 128PiB || 64-bit only
|}

Feel free to choose between these modes as you see fit; this page will describe all of them. Note that in 64-bit systems, Sv39 is more than enough for most hobby operating systems (though it is not much more difficult to go further).

=== Sv32 ===

Sv32 is the only available paging mode for a 32 bit system, it provides 32 bit virtual addresses, and 34 bit physical addresses.

'''Address and PTE Layouts'''
{| class="wikitable"
|+Sv32 virtual address
!Bit Range (inclusive)
!Length (bits)
!Description
|-
|0-11
|12
|Page offset
|-
|12-21
|10
|Page VPN (VPN[0])
|-
|22-31
|10
|Megapage VPN (VPN[0])
|}
{| class="wikitable"
|+Sv32 physical address
!Bit Range (inclusive)
!Length (bits)
!Description
|-
|0-11
|12
|Page offset
|-
|12-21
|10
|PPN[0]
|-
|22-33
|12
|PPN[1]
|}
{| class="wikitable"
|+Sv32 page table entry layout
!Bit Range (inclusive)
!Length (bits)
!Description
|-
|0
|1
|Valid flag (V)
|-
|1
|1
|Readable flag (R)
|-
|2
|1
|Writable flag (W)
|-
|3
|1
|Executable flag (X)
|-
|4
|1
|U-mode accessible flag (U)
|-
|5
|1
|Global flag (G)
|-
|6
|1
|Accessed flag (A)
|-
|7
|1
|Dirty flag (D)
|-
|8-9
|2
|RSW
|-
|10-19
|10
|<nowiki>PPN[0]</nowiki>
|-
|20-31
|12
|<nowiki>PPN[1]</nowiki>
|}

=== Sv39 ===

Sv39 is the simplest paging mode for 64-bit systems (though larger modes are not too much more difficult to implement). It supports the standard 4KiB pages, as well as 2MiB megapages and 1GiB gigapages.

TODO: actually describe what a page table looks like, and also PTE's RWX encoding

==== Address and PTE Layouts ====

{| class="wikitable mw-collapsible"
|+ Sv39 virtual address
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0-11 || 12 || Page offset
|-
| 12-20 || 9 || Page VPN (<nowiki>VPN[0]</nowiki>)
|-
| 21-29 || 9 || Megapage VPN (<nowiki>VPN[1]</nowiki>)
|-
| 30-38 || 9 || Gigapage VPN (<nowiki>VPN[2]</nowiki>)
|}

{| class="wikitable mw-collapsible"
|+ Sv39 physical address
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0-11 || 12 || Page offset
|-
| 12-20 || 9 || <nowiki>PPN[0]</nowiki>
|-
| 21-29 || 9 || <nowiki>PPN[1]</nowiki>
|-
| 30-55 || 26 || <nowiki>PPN[2]</nowiki>
|}

{| class="wikitable mw-collapsible"
|+ Sv39 page table entry layout
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0 || 1 || Valid flag (V)
|-
| 1 || 1 || Readable flag (R)
|-
| 2 || 1 || Writable flag (W)
|-
| 3 || 1 || Executable flag (X)
|-
| 4 || 1 || U-mode accessible flag (U)
|-
| 5 || 1 || Global flag (G)
|-
| 6 || 1 || Accessed flag (A)
|-
| 7 || 1 || Dirty flag (D)
|-
| 8-9 || 2 || RSW
|-
| 10-18 || 9 || <nowiki>PPN[0]</nowiki>
|-
| 19-27 || 9 || <nowiki>PPN[1]</nowiki>
|-
| 28-53 || 26 || <nowiki>PPN[2]</nowiki>
|-
| 54-60 || 7 || Reserved
|-
| 61-62 || 2 || PBMT (TODO)
|-
| 63 || 1 || N bit (TODO)
|}

=== Sv48 ===

TODO: Explain

==== Address and PTE Layouts ====

{| class="wikitable mw-collapsible"
|+ Sv48 virtual address
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0-11 || 12 || Page offset
|-
| 12-20 || 9 || Page VPN (<nowiki>VPN[0]</nowiki>)
|-
| 21-29 || 9 || Megapage VPN (<nowiki>VPN[1]</nowiki>)
|-
| 30-38 || 9 || Gigapage VPN (<nowiki>VPN[2]</nowiki>)
|-
| 39-47 || 9 || (<nowiki>VPN[3]</nowiki>)
|}

{| class="wikitable mw-collapsible"
|+ Sv48 physical address
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0-11 || 12 || Page offset
|-
| 12-20 || 9 || (<nowiki>PPN[0]</nowiki>)
|-
| 21-29 || 9 || (<nowiki>PPN[1]</nowiki>)
|-
| 30-38 || 9 || (<nowiki>PPN[2]</nowiki>)
|-
| 39-47 || 9 || (<nowiki>PPN[3]</nowiki>)
|}

{| class="wikitable mw-collapsible"
|+ Sv48 page table entry layout
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0 || 1 || Valid flag (V)
|-
| 1 || 1 || Readable flag (R)
|-
| 2 || 1 || Writable flag (W)
|-
| 3 || 1 || Executable flag (X)
|-
| 4 || 1 || U-mode accessible flag (U)
|-
| 5 || 1 || Global flag (G)
|-
| 6 || 1 || Accessed flag (A)
|-
| 7 || 1 || Dirty flag (D)
|-
| 8-9 || 2 || RSW
|-
| 10-18 || 9 || <nowiki>PPN[0]</nowiki>
|-
| 19-27 || 9 || <nowiki>PPN[1]</nowiki>
|-
| 28-36 || 9 || <nowiki>PPN[2]</nowiki>
|-
| 37-53 || 17 || <nowiki>PPN[3]</nowiki>
|-
| 54-60 || 7 || Reserved
|-
| 61-62 || 2 || PBMT (TODO)
|-
| 63 || 1 || N bit (TODO)
|}

=== Sv57 ===

TODO

== Enabling Paging ==

TODO: Explain better

Paging on RISC-V is split into 4 different modes, 32 bit, 39 bit, 48 bit, and 57 bit. 32 bit is only available on 32 bit systems, and not available on 64 bit systems.
Paging is handled by the `SATP` CSR which contains 3 separate sections, the PPN(Physical Page Number) which is similar to the physical address, the ASID(Address Space Identifier), and finally, the Mode. To enable paging you need to write a paging mode into the Mode section of the `SATP` register. On 64 bits you can write 0 for no paging, 8 for Sv39, 9 for Sv48, 10 for Sv57, and in the future 11 will be available for 64 bits. On 32 bits you can write 0 for no paging, or 1 for Sv32.

Rust example code:

32 bits
<syntaxhighlight lang="rust" line>
pub unsafe fn enable_paging(root_page_table: usize) {
let ppn = root_page_table >> 12;
let mode = 1 << 31;

let write = mode | ppn;

core::arch::asm(
"csrw satp, {}",
in(reg) write
);
}
</syntaxhighlight>

64 bits
<syntaxhighlight lang="rust" line>
pub unsafe fn enable_paging(root_page_table: usize, mode: u8) {
let ppn = root_page_table >> 12;
let new_mode = (mode & 0xf) << 60;

let write = mode | ppn;

core::arch::asm(
"csrw satp, {}",
in(reg) write
);
}
</syntaxhighlight>

RISC-V/Paging

2023-11-02T23:42:06Z

ThePuzzlemaker: Add to Category:RISC-V

[[Category:RISC-V]]
Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp | <code>satp</code> CSR]]. This article will describe these steps.

Paging type can be determined at runtime using the device tree, its typically located in the CPU specific nodes, such as `cpu@x` where x denotes which number of CPU it is, it will be located under the `mmu-type` property in the form of a string such as `riscv,svY` is either "32", "39", "48", or "57" depending on paging type.

== Terminology ==

There are many acronyms and other terms that are used in the RISC-V specification which, for the purpose of brevity and consistency, will be used in this article as well. I will assume a baseline knowledge of the purpose and basics of paging and virtual addressing.

=== PPNs and VPNs ===

A physical page number (or PPN) is a unique, page-aligned identifier for a page in physical memory. The number of PPN segments for an address will depend on the paging mode.

To construct a PPN from a physical address, you can simply (logically, not arithmetically) shift the value right by 12 bits (as 2**12 = 4096). Note that this operation will truncate the offset into the page, if the address was not page-aligned.

A virtual page number (or VPN) is very similar to a PPN, but in the virtual address space. Again, the number of VPN segments for a virtual address will depend on the paging mode.

=== RSW ===
Bits marked as RSW indicate that they can be written, read, and handled in any way the OS wants without causing issues. These can be used as OS-specific flags.

== RISC-V Page Table Layout ==

There are various paging modes available in the RISC-V ISA, differing by the number of virtual address bits:
{| class="wikitable"
|-
! Name !! Memory Size !! SXLEN
|-
| Sv32 || 4GiB || 32-bit only
|-
| Sv39 || 512GiB || 64-bit only
|-
| Sv48 || 256TiB || 64-bit only
|-
| Sv57 || 128PiB || 64-bit only
|}

Feel free to choose between these modes as you see fit; this page will describe all of them. Note that in 64-bit systems, Sv39 is more than enough for most hobby operating systems (though it is not much more difficult to go further).

=== Sv32 ===

Sv32 is the only available paging mode for a 32 bit system, it provides 32 bit virtual addresses, and 34 bit physical addresses.

'''Address and PTE Layouts'''
{| class="wikitable"
|+Sv32 virtual address
!Bit Range (inclusive)
!Length (bits)
!Description
|-
|0-11
|12
|Page offset
|-
|12-21
|10
|Page VPN (VPN[0])
|-
|22-31
|10
|Megapage VPN (VPN[0])
|}
{| class="wikitable"
|+Sv32 physical address
!Bit Range (inclusive)
!Length (bits)
!Description
|-
|0-11
|12
|Page offset
|-
|12-21
|10
|PPN[0]
|-
|22-33
|12
|PPN[1]
|}
{| class="wikitable"
|+Sv32 page table entry layout
!Bit Range (inclusive)
!Length (bits)
!Description
|-
|0
|1
|Valid flag (V)
|-
|1
|1
|Readable flag (R)
|-
|2
|1
|Writable flag (W)
|-
|3
|1
|Executable flag (X)
|-
|4
|1
|U-mode accessible flag (U)
|-
|5
|1
|Global flag (G)
|-
|6
|1
|Accessed flag (A)
|-
|7
|1
|Dirty flag (D)
|-
|8-9
|2
|RSW
|-
|10-19
|10
|<nowiki>PPN[0]</nowiki>
|-
|20-31
|12
|<nowiki>PPN[1]</nowiki>
|}

=== Sv39 ===

Sv39 is the simplest paging mode for 64-bit systems (though larger modes are not too much more difficult to implement). It supports the standard 4KiB pages, as well as 2MiB megapages and 1GiB gigapages.

TODO: actually describe what a page table looks like, and also PTE's RWX encoding

==== Address and PTE Layouts ====

{| class="wikitable mw-collapsible"
|+ Sv39 virtual address
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0-11 || 12 || Page offset
|-
| 12-20 || 9 || Page VPN (<nowiki>VPN[0]</nowiki>)
|-
| 21-29 || 9 || Megapage VPN (<nowiki>VPN[1]</nowiki>)
|-
| 30-38 || 9 || Gigapage VPN (<nowiki>VPN[2]</nowiki>)
|}

{| class="wikitable mw-collapsible"
|+ Sv39 physical address
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0-11 || 12 || Page offset
|-
| 12-20 || 9 || <nowiki>PPN[0]</nowiki>
|-
| 21-29 || 9 || <nowiki>PPN[1]</nowiki>
|-
| 30-55 || 26 || <nowiki>PPN[2]</nowiki>
|}

{| class="wikitable mw-collapsible"
|+ Sv39 page table entry layout
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0 || 1 || Valid flag (V)
|-
| 1 || 1 || Readable flag (R)
|-
| 2 || 1 || Writable flag (W)
|-
| 3 || 1 || Executable flag (X)
|-
| 4 || 1 || U-mode accessible flag (U)
|-
| 5 || 1 || Global flag (G)
|-
| 6 || 1 || Accessed flag (A)
|-
| 7 || 1 || Dirty flag (D)
|-
| 8-9 || 2 || RSW
|-
| 10-18 || 9 || <nowiki>PPN[0]</nowiki>
|-
| 19-27 || 9 || <nowiki>PPN[1]</nowiki>
|-
| 28-53 || 26 || <nowiki>PPN[2]</nowiki>
|-
| 54-60 || 7 || Reserved
|-
| 61-62 || 2 || PBMT (TODO)
|-
| 63 || 1 || N bit (TODO)
|}

=== Sv48 ===

TODO: Explain

==== Address and PTE Layouts ====

{| class="wikitable mw-collapsible"
|+ Sv48 virtual address
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0-11 || 12 || Page offset
|-
| 12-20 || 9 || Page VPN (<nowiki>VPN[0]</nowiki>)
|-
| 21-29 || 9 || Megapage VPN (<nowiki>VPN[1]</nowiki>)
|-
| 30-38 || 9 || Gigapage VPN (<nowiki>VPN[2]</nowiki>)
|-
| 39-47 || 9 || (<nowiki>VPN[3]</nowiki>)
|}

{| class="wikitable mw-collapsible"
|+ Sv48 physical address
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0-11 || 12 || Page offset
|-
| 12-20 || 9 || (<nowiki>PPN[0]</nowiki>)
|-
| 21-29 || 9 || (<nowiki>PPN[1]</nowiki>)
|-
| 30-38 || 9 || (<nowiki>PPN[2]</nowiki>)
|-
| 39-47 || 9 || (<nowiki>PPN[3]</nowiki>)
|}

{| class="wikitable mw-collapsible"
|+ Sv48 page table entry layout
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0 || 1 || Valid flag (V)
|-
| 1 || 1 || Readable flag (R)
|-
| 2 || 1 || Writable flag (W)
|-
| 3 || 1 || Executable flag (X)
|-
| 4 || 1 || U-mode accessible flag (U)
|-
| 5 || 1 || Global flag (G)
|-
| 6 || 1 || Accessed flag (A)
|-
| 7 || 1 || Dirty flag (D)
|-
| 8-9 || 2 || RSW
|-
| 10-18 || 9 || <nowiki>PPN[0]</nowiki>
|-
| 19-27 || 9 || <nowiki>PPN[1]</nowiki>
|-
| 28-36 || 9 || <nowiki>PPN[2]</nowiki>
|-
| 37-53 || 17 || <nowiki>PPN[3]</nowiki>
|-
| 54-60 || 7 || Reserved
|-
| 61-62 || 2 || PBMT (TODO)
|-
| 63 || 1 || N bit (TODO)
|}

=== Sv57 ===

TODO

== Enabling Paging ==

TODO: Explain better

Paging on RISC-V is split into 4 different modes, 32 bit, 39 bit, 48 bit, and 57 bit. 32 bit is only available on 32 bit systems, and not available on 64 bit systems.
Paging is handled by the `SATP` CSR which contains 3 separate sections, the PPN(Physical Page Number) which is similar to the physical address, the ASID(Address Space Identifier), and finally, the Mode. To enable paging you need to write a paging mode into the Mode section of the `SATP` register. On 64 bits you can write 0 for no paging, 8 for Sv39, 9 for Sv48, 10 for Sv57, and in the future 11 will be available for 64 bits. On 32 bits you can write 0 for no paging, or 1 for Sv32.

Rust example code:

32 bits
<syntaxhighlight lang="rust" line>
pub unsafe fn enable_paging(root_page_table: usize) {
let ppn = root_page_table >> 12;
let mode = 1 << 31;

let write = mode | ppn;

core::arch::asm(
"csrw satp, {}",
in(reg) write
);
}
</syntaxhighlight>

64 bits
<syntaxhighlight lang="rust" line>
pub unsafe fn enable_paging(root_page_table: usize, mode: u8) {
let ppn = root_page_table >> 12;
let new_mode = (mode & 0xf) << 60;

let write = mode | ppn;

core::arch::asm(
"csrw satp, {}",
in(reg) write
);
}
</syntaxhighlight>

RISC-V/Paging

2022-11-24T03:11:35Z

ThePuzzlemaker:

Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp | <code>satp</code> CSR]]. This article will describe these steps.

== Terminology ==

There are many acronyms and other terms that are used in the RISC-V specification which, for the purpose of brevity and consistency, will be used in this article as well. I will assume a baseline knowledge of the purpose and basics of paging and virtual addressing.

=== PPNs and VPNs ===

A physical page number (or PPN) is a unique, page-aligned identifier for a page in physical memory. The number of PPN segments for an address will depend on the paging mode.

To construct a PPN from a physical address, you can simply (logically, not arithmetically) shift the value right by 12 bits (as 2**12 = 4096). Note that this operation will truncate the offset into the page, if the address was not page-aligned.

A virtual page number (or VPN) is very similar to a PPN, but in the virtual address space. Again, the number of VPN segments for a virtual address will depend on the paging mode.

== RISC-V Page Table Layout ==

There are various paging modes available in the RISC-V ISA, differing by the number of virtual address bits:
{| class="wikitable"
|-
! Name !! Memory Size !! SXLEN
|-
| Sv32 || 4GiB || 32-bit only
|-
| Sv39 || 512GiB || 64-bit only
|-
| Sv48 || 256TiB || 64-bit only
|-
| Sv57 || 128PiB || 64-bit only
|}

Feel free to choose between these modes as you see fit; this page will describe all of them. Note that in 64-bit systems, Sv39 is more than enough for most hobby operating systems (though it is not much more difficult to go further).

=== Sv32 ===

TODO

=== Sv39 ===

Sv39 is the simplest paging mode for 64-bit systems (though larger modes are not too much more difficult to implement). It supports the standard 4KiB pages, as well as 2MiB megapages and 1GiB gigapages.

TODO: actually describe what a page table looks like, and also PTE's RWX encoding

==== Address and PTE Layouts ====

{| class="wikitable mw-collapsible"
|+ Sv39 virtual address
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0-11 || 12 || Page offset
|-
| 12-20 || 9 || Page VPN (<nowiki>VPN[0]</nowiki>)
|-
| 21-29 || 9 || Megapage VPN (<nowiki>VPN[1]</nowiki>)
|-
| 30-38 || 9 || Gigapage VPN (<nowiki>VPN[2]</nowiki>)
|}

{| class="wikitable mw-collapsible"
|+ Sv39 physical address
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0-11 || 12 || Page offset
|-
| 12-20 || 9 || <nowiki>PPN[0]</nowiki>
|-
| 21-29 || 9 || <nowiki>PPN[1]</nowiki>
|-
| 30-55 || 26 || <nowiki>PPN[2]</nowiki>
|}

{| class="wikitable mw-collapsible"
|+ Sv39 page table entry layout
|-
! Bit Range (inclusive) !! Length (bits) !! Description
|-
| 0 || 1 || Valid flag (V)
|-
| 1 || 1 || Readable flag (R)
|-
| 2 || 1 || Writable flag (W)
|-
| 3 || 1 || Executable flag (X)
|-
| 4 || 1 || U-mode accessible flag (U)
|-
| 5 || 1 || Global flag (G)
|-
| 6 || 1 || Accessed flag (A)
|-
| 7 || 1 || Dirty flag (D)
|-
| 8-9 || 2 || RSW (TODO)
|-
| 10-18 || 9 || <nowiki>PPN[0]</nowiki>
|-
| 19-27 || 9 || <nowiki>PPN[1]</nowiki>
|-
| 28-53 || 26 || <nowiki>PPN[2]</nowiki>
|-
| 54-60 || 7 || Reserved
|-
| 61-62 || 2 || PBMT (TODO)
|-
| 63 || 1 || N bit (TODO)
|}

=== Sv48 ===

TODO

=== Sv57 ===

TODO

== Enabling Paging ==

TODO

RISC-V/Paging

2022-11-24T02:53:52Z

ThePuzzlemaker: Describe PPNs and VPNs

RISC-V/Paging

2022-11-23T21:21:10Z

ThePuzzlemaker: Created page with "Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the <code>satp</code> CSR. This article will describe these steps. == RISC-V Page Table Layout == There are various paging strategies available in the RISC-V ISA, differing by the number of virtual address bits: {| class="wikitable" |- ! Name !! Memory Size !! SXLEN |- | Sv32 || 4GiB || 32-bit only |- | Sv39 || 512GiB || 64-bit only |- |..."

Paging in RISC-V can be enabled by first setting up a page table, then pointing the CPU to that page table via the [[RISC-V/CSR#satp | <code>satp</code> CSR]]. This article will describe these steps.

== RISC-V Page Table Layout ==

There are various paging strategies available in the RISC-V ISA, differing by the number of virtual address bits:
{| class="wikitable"
|-
! Name !! Memory Size !! SXLEN
|-
| Sv32 || 4GiB || 32-bit only
|-
| Sv39 || 512GiB || 64-bit only
|-
| Sv48 || 256TiB || 64-bit only
|-
| Sv57 || 128PiB || 64-bit only
|}

Feel free to choose between these strategies as you see fit; this page will describe all of them. Note that in 64-bit systems, Sv39 is more than enough for most hobby operating systems (though it is not much more difficult to go further).

=== Sv32 ===

TODO

=== Sv39 ===

TODO

=== Sv48 ===

TODO

=== Sv57 ===

TODO

== Enabling Paging ==

TODO

Main Page

2022-11-23T20:11:02Z

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