FriendOS Wiki - User contributions [en]

Intel 64 Architecture

2025-07-12T02:53:31Z

TheCatgirls: /* 64-bit Mode */ - fixed an unconverted italics

= Architecture =

The Intel 64 Architecture is a 64-bit extension of the 32-bit [[x86]] [[IA-32]] architecture. It was introduced around 2004, reimplementing [[AMD64]], AMD's 64-bit extension.

Both [[AMD64]] and Intel 64 Architecture (from henceforth referred to as I64A; Do not confuse with [[Itanium]], referred to as [[Itanium|IA64]].) are collectively referred to as [[x86_64]], and commonly as [[x86_64|x64]], or [[x86_64|64bit x86]].

I64A introduces a new [[x86 Operating Mode]] to the existing set already present in [[IA-32]] referred to as [[IA-32e]], which has two sub-modes, [[IA-32e Compatibility Mode]] and [[IA-32e 64bit Mode]].

= Summary =

I64A is the most common [[x86]] architecture in use today, and as such, we will detail things present in I64A that are also present in other [[x86]] architectures. We will describe average somewhat modern Intel CPU here.

When the system boots up, the [[Intel Managemenet Engine]] (IME) initializes the chipset, then loads the [[Motherboard Firmware]] from its ROM, and jumps to it. The [[Motherboard Firmware]] then initializes the computer, [[Power-On Self Test|POSTs]], and executes its defined [[Firmware Interface]] to load a [[Bootloader]].

The two main [[Firmware Interface|Firmware Interfaces]] are [[Basic Input-Output System|BIOS]] and [[Unified Extensible Firmware Interface|UEFI]]. [[Basic Input-Output System|BIOS]] is older, back from [[Disk Operating System|DOS]] days. [[Unified Extensible Firmware Interface|UEFI]] is newer, and the current preferred standard for most non-legacy applications.

I64A has several [[x86 Operating Mode|operating modes]].
* [[Protected Mode]] (native)
* [[Real-address Mode]] (emulated)
* [[System-management Mode]] (SMM)
* [[Compatibility Mode]] (IA-32e)
* [[64-bit Mode]] (IA-32e)

===== Protected Mode =====
Main article: [[Protected Mode]]
32-bit [[General-Purpose Register|GPR]] set. Instructions default to 32bit (operand size and address size). Addresses consist of a 16-bit [[Segment Selector]] and 32-bit offset.

Protected Mode (henceforth referred to as PM) supports both [[Paging]] and [[Segmentation]].
[[Segmentation]] is ''mandatory'', though it can be configured to be essentially a no-op, a so-called [[Flat Segmentation Model]], eg. if you want to use [[Paging]] only.

Segmentation is configured though a [[Global Descriptor Table]].
===== Real-address Mode =====
Main article: [[Real-address Mode]]
16-bit [[General-Purpose Register|GPR]] set. Essentially just emulates an [[8086]]. Thus, 16-bit addresses with 4-bit [[Segment Registers]] for [[Segment Selector|Segment Selection]]. Do note that ''[[Segment Registers]]'' are different from but interconnected with [[Segmentation]]! [[Segment Selector|Segment Selection]] allows for the existence of several separate address spaces ''only'', it is ''not'' a form of protected memory like [[Protected Mode|PM]]'s [[Segmentation]] - you ''cannot'' configure memory protection (which [[Protected Mode]] gets its name from) controls.
===== System-management Mode =====
Main article: [[System-management Mode]]
It's a part of the APIs the [[Motherboard Firmware]] implementation uses for implementing certain features. Namely, the CPU switches to this mode when it receives a [[System Management Interrupt]], that is, a certain [[Hardware Interrupt]] on the [[System Management Interrupt|SMI]] line (which is kind of like the [[Non-Maskable Interrupt|NMI]] line).

Not to be confused with the [[System Management Module]]. Thanks Intel.
===== Compatibility Mode =====
===== 64-bit Mode =====
In 64-bit mode, segmentation is ''mostly'' disabled. The [[Segment Register|segment registers]] still need to hold a valid [[Segment Selector]] for a valid [[Segment Entry]], but the base field is not used in address calculations.
Do note that there are [[GSBASE]] and [[FSBASE]] [[Model Specific Register|MSRs]] present which ''are'' used in [[Effective Address]] calculations if the instruction has a FS or GS [[Segment Override Instruction Prefix]]. Those [[Model Specific Register|MSRs]] are written to with the base of the selected segment when their respective segment registers are written to (TODO verify, manual doesn't state as such)

[[Category:X86]]

Apic

2024-12-21T07:00:41Z

TheCatgirls: TheCatgirls moved page Apic to APIC: Uppercase :)

#REDIRECT [[APIC]]

APIC

2024-12-21T07:00:41Z

TheCatgirls: TheCatgirls moved page Apic to APIC: Uppercase :)

==LAPIC and IOAPIC==

The Advanced Programmable Interrupter Controller(APIC) is a interrupt controller designed to replace the 8529 Intel programmable interrupt controller(PIC) that had been standard up until this point. The reason for this replacement was two fold. Multiprocessor systems where becoming more common and the old PIC was unable to control which CPU cores would be sent interrupts, Along with the APIC being capable of sending Inter-Processor-Interrupts(IPI).

This allowed for OS's to have more fine grained control over their interrupts and allowed for better hardware delegation of interrupts allowing certain CPU cores to handle certain interrupts. The design of the APIC is simple really it's split into two pieces the Local APIC(LAPIC) and the IOAPIC. With each LAPIC and IOAPIC having an ID number on their dedicated APIC bus.

The Local APIC is a CPU core local interrupt controller, each CPU core has it's own LAPIC, these can handle their own timer interrupts and external Hardware Interrupts that are sent via the IOAPIC. The IOAPIC on the other hand is connected to external devices([[PIT]],[[HPET]],[[PS/2]] Controller, etc...) and through the use of redirection tables it can be programmed with a LAPIC ID in each Interrupt redirection table entry. This ID controls which LAPIC and thus which core will service this hardware interrupt. It is quite common for a system to have one IOAPIC however plenty of systems may two or more IOAPICs you should parse the MP tables or the [[ACPI]] [[MADT]] table to ensure all IOAPICs are found.

===Please Note===
The MP specification is an old spec and though it will contain the information needed for the IOAPIC and LAPIC. It may not be present on newer systems and the ACPI tables should be preferred over the MP spec wherever possible.

==LAPIC==
Support for the local APIC can be queried using two different methods. One would be using CPUID <code>EDX=0x00000001</code>. Or you could parse the [[MP Tables]] or the [[ACPI]] [[MADT]] table(Which you would likely want to do anyway for SMP). You could also check the APIC Base MSR and assume if those exist that the LAPIC is present at the "default" physical address of <code>0xfee00000</code>. However the best way would be to check the CPUID, then parse the [[MP Tables|MP]] or the ACPI [[MADT]] table to determine both the if APIC is supported and get the LAPIC Physical address from the [[MP Tables|MP]]/[[MADT]] Table. If you wish to double check this base address you can also check the APIC Base MSR(`0x1b`).

===Register Layout===

TODO:

==IOAPIC==
The IOAPIC can be queried in multiple different ways one is to assume that if the LAPIC exists that at least one IOAPIC exists at the "default" physical address of <code>0xfec00000</code>. However again this isn't ideal and you should attempt to parse either the [[MP Tables]] or the [[ACPI]] [[MADT]] Tables. To Ensure you have the correct physical addresses and have found all IOAPICs in this system.

===Register Layout===
todo:
{| class="wikitable"
|+
|}

== Programming LAPIC/IOAPIC ==
When Programming these devices their memory addresses should always be marked as non-cacheable to ensure proper operation of the devices as caching them could produce strange and undesired results due to cached values being read rather than the actual true values of the MMIO registers. In the below code we are also going to assume that everything is at it's "default" standard physical address in memory and that if paging is active it's just a simple identity map paging i.e. Virtual Address = Physical Address.

In your kernel you are going to want to parse ACPI structures and map these physical addresses in a way that makes sense for your [[VMM]].

=== IOAPIC: ===
Below is an example of programming the IOAPIC to route GSI 2 typically ISA IRQ 0(PIT Timer) to CPU 0 with the interrupt vector set to <code>0x20</code> this is because the IOAPIC operates on register select and window model of programming meaning that <code>base + 0</code> = the register to select. and <code>base + 0x10</code> = the selected register.

Each Interrupt redirection entry is split into two 32bit registers. The lower bits contains data such as which IDT vector will be called for this interrupt, polarity, delivery mode, edge or level triggered, masked, etc...

While the upper 32bits contain the the LAPIC ID that this interrupt will be sent to. Depending on the setting of bit 11 of the lower 32bit. See <syntaxhighlight lang="c">
void ioapic_init() {
volatile uint32_t *ioapic = (uint32_t*)0xfec00000;
/*Timer Interrupt for QEMU*/
base[0] = 0x14; /*GSI Interrupt 2 Most commonly PIT/HPET timer*/
base[4] = 0x20; /*Interrupt Vector i.e. IDT vector 0x20 will be called for this*/
base[0] = 0x14; /*GSI Interrupt 2 upper 32bit*/
base[4] = 0x00;
}
</syntaxhighlight>

==Links==
[https://pdos.csail.mit.edu/6.828/2016/readings/ia32/ioapic.pdf IOAPIC datasheet from MIT.edu]

[https://uefi.org/sites/default/files/resources/ACPI%20Spec%206%205%20Aug29.pdf ACPI Spec]

[https://pdos.csail.mit.edu/6.828/2018/readings/ia32/MPspec.pdf MPspec Datasheet from MIT.edu]

[https://cdrdv2.intel.com/v1/dl/getContent/671200 Intel SDM Full(Volume 3 chapter 12 for APIC Documentation)]

[https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/40332.pdf AMD SDM(Volume 2 chapter 16 for APIC Documentation)]

Intel 64 Architecture

2024-12-19T15:16:40Z

TheCatgirls: Fix link

= Architecture =

The Intel 64 Architecture is a 64-bit extension of the 32-bit [[x86]] [[IA-32]] architecture. It was introduced around 2004, reimplementing [[AMD64]], AMD's 64-bit extension.

Both [[AMD64]] and Intel 64 Architecture (from henceforth referred to as I64A; Do not confuse with [[Itanium]], referred to as [[Itanium|IA64]].) are collectively referred to as [[x86_64]], and commonly as [[x86_64|x64]], or [[x86_64|64bit x86]].

I64A introduces a new [[x86 Operating Mode]] to the existing set already present in [[IA-32]] referred to as [[IA-32e]], which has two sub-modes, [[IA-32e Compatibility Mode]] and [[IA-32e 64bit Mode]].

= Summary =

I64A is the most common [[x86]] architecture in use today, and as such, we will detail things present in I64A that are also present in other [[x86]] architectures. We will describe average somewhat modern Intel CPU here.

When the system boots up, the [[Intel Managemenet Engine]] (IME) initializes the chipset, then loads the [[Motherboard Firmware]] from its ROM, and jumps to it. The [[Motherboard Firmware]] then initializes the computer, [[Power-On Self Test|POSTs]], and executes its defined [[Firmware Interface]] to load a [[Bootloader]].

The two main [[Firmware Interface|Firmware Interfaces]] are [[Basic Input-Output System|BIOS]] and [[Unified Extensible Firmware Interface|UEFI]]. [[Basic Input-Output System|BIOS]] is older, back from [[Disk Operating System|DOS]] days. [[Unified Extensible Firmware Interface|UEFI]] is newer, and the current preferred standard for most non-legacy applications.

I64A has several [[x86 Operating Mode|operating modes]].
* [[Protected Mode]] (native)
* [[Real-address Mode]] (emulated)
* [[System-management Mode]] (SMM)
* [[Compatibility Mode]] (IA-32e)
* [[64-bit Mode]] (IA-32e)

===== Protected Mode =====
Main article: [[Protected Mode]]
32-bit [[General-Purpose Register|GPR]] set. Instructions default to 32bit (operand size and address size). Addresses consist of a 16-bit [[Segment Selector]] and 32-bit offset.

Protected Mode (henceforth referred to as PM) supports both [[Paging]] and [[Segmentation]].
[[Segmentation]] is ''mandatory'', though it can be configured to be essentially a no-op, a so-called [[Flat Segmentation Model]], eg. if you want to use [[Paging]] only.

Segmentation is configured though a [[Global Descriptor Table]].
===== Real-address Mode =====
Main article: [[Real-address Mode]]
16-bit [[General-Purpose Register|GPR]] set. Essentially just emulates an [[8086]]. Thus, 16-bit addresses with 4-bit [[Segment Registers]] for [[Segment Selector|Segment Selection]]. Do note that ''[[Segment Registers]]'' are different from but interconnected with [[Segmentation]]! [[Segment Selector|Segment Selection]] allows for the existence of several separate address spaces ''only'', it is ''not'' a form of protected memory like [[Protected Mode|PM]]'s [[Segmentation]] - you ''cannot'' configure memory protection (which [[Protected Mode]] gets its name from) controls.
===== System-management Mode =====
Main article: [[System-management Mode]]
It's a part of the APIs the [[Motherboard Firmware]] implementation uses for implementing certain features. Namely, the CPU switches to this mode when it receives a [[System Management Interrupt]], that is, a certain [[Hardware Interrupt]] on the [[System Management Interrupt|SMI]] line (which is kind of like the [[Non-Maskable Interrupt|NMI]] line).

Not to be confused with the [[System Management Module]]. Thanks Intel.
===== Compatibility Mode =====
===== 64-bit Mode =====
In 64-bit mode, segmentation is ''mostly'' disabled. The [[Segment Register|segment registers]] still need to hold a valid [[Segment Selector]] for a valid [[Segment Entry]], but the base field is not used in address calculations.
Do note that there are [[GSBASE]] and [[FSBASE]] [[Model Specific Register|MSRs]] present which _are_ used in [[Effective Address]] calculations if the instruction has a FS or GS [[Segment Override Instruction Prefix]]. Those [[Model Specific Register|MSRs]] are written to with the base of the selected segment when their respective segment registers are written to (TODO verify, manual doesn't state as such)

[[Category:X86]]

Intel 64 Architecture

2024-12-19T15:16:09Z

TheCatgirls: 64-bit Mode expanded

= Architecture =

The Intel 64 Architecture is a 64-bit extension of the 32-bit [[x86]] [[IA-32]] architecture. It was introduced around 2004, reimplementing [[AMD64]], AMD's 64-bit extension.

Both [[AMD64]] and Intel 64 Architecture (from henceforth referred to as I64A; Do not confuse with [[Itanium]], referred to as [[Itanium|IA64]].) are collectively referred to as [[x86_64]], and commonly as [[x86_64|x64]], or [[x86_64|64bit x86]].

I64A introduces a new [[x86 Operating Mode]] to the existing set already present in [[IA32]] referred to as [[IA-32e]], which has two sub-modes, [[IA-32e Compatibility Mode]] and [[IA-32e 64bit Mode]].

= Summary =

I64A is the most common [[x86]] architecture in use today, and as such, we will detail things present in I64A that are also present in other [[x86]] architectures. We will describe average somewhat modern Intel CPU here.

When the system boots up, the [[Intel Managemenet Engine]] (IME) initializes the chipset, then loads the [[Motherboard Firmware]] from its ROM, and jumps to it. The [[Motherboard Firmware]] then initializes the computer, [[Power-On Self Test|POSTs]], and executes its defined [[Firmware Interface]] to load a [[Bootloader]].

The two main [[Firmware Interface|Firmware Interfaces]] are [[Basic Input-Output System|BIOS]] and [[Unified Extensible Firmware Interface|UEFI]]. [[Basic Input-Output System|BIOS]] is older, back from [[Disk Operating System|DOS]] days. [[Unified Extensible Firmware Interface|UEFI]] is newer, and the current preferred standard for most non-legacy applications.

I64A has several [[x86 Operating Mode|operating modes]].
* [[Protected Mode]] (native)
* [[Real-address Mode]] (emulated)
* [[System-management Mode]] (SMM)
* [[Compatibility Mode]] (IA-32e)
* [[64-bit Mode]] (IA-32e)

===== Protected Mode =====
Main article: [[Protected Mode]]
32-bit [[General-Purpose Register|GPR]] set. Instructions default to 32bit (operand size and address size). Addresses consist of a 16-bit [[Segment Selector]] and 32-bit offset.

Protected Mode (henceforth referred to as PM) supports both [[Paging]] and [[Segmentation]].
[[Segmentation]] is ''mandatory'', though it can be configured to be essentially a no-op, a so-called [[Flat Segmentation Model]], eg. if you want to use [[Paging]] only.

Segmentation is configured though a [[Global Descriptor Table]].
===== Real-address Mode =====
Main article: [[Real-address Mode]]
16-bit [[General-Purpose Register|GPR]] set. Essentially just emulates an [[8086]]. Thus, 16-bit addresses with 4-bit [[Segment Registers]] for [[Segment Selector|Segment Selection]]. Do note that ''[[Segment Registers]]'' are different from but interconnected with [[Segmentation]]! [[Segment Selector|Segment Selection]] allows for the existence of several separate address spaces ''only'', it is ''not'' a form of protected memory like [[Protected Mode|PM]]'s [[Segmentation]] - you ''cannot'' configure memory protection (which [[Protected Mode]] gets its name from) controls.
===== System-management Mode =====
Main article: [[System-management Mode]]
It's a part of the APIs the [[Motherboard Firmware]] implementation uses for implementing certain features. Namely, the CPU switches to this mode when it receives a [[System Management Interrupt]], that is, a certain [[Hardware Interrupt]] on the [[System Management Interrupt|SMI]] line (which is kind of like the [[Non-Maskable Interrupt|NMI]] line).

Not to be confused with the [[System Management Module]]. Thanks Intel.
===== Compatibility Mode =====
===== 64-bit Mode =====
In 64-bit mode, segmentation is ''mostly'' disabled. The [[Segment Register|segment registers]] still need to hold a valid [[Segment Selector]] for a valid [[Segment Entry]], but the base field is not used in address calculations.
Do note that there are [[GSBASE]] and [[FSBASE]] [[Model Specific Register|MSRs]] present which _are_ used in [[Effective Address]] calculations if the instruction has a FS or GS [[Segment Override Instruction Prefix]]. Those [[Model Specific Register|MSRs]] are written to with the base of the selected segment when their respective segment registers are written to (TODO verify, manual doesn't state as such)

[[Category:X86]]

IA32 Manual Conventions

2024-12-19T15:09:27Z

TheCatgirls: Add to x86 category

Bit number 0 is the first, [[Least Significant Bit]].
Bit ranges are written inclusive. Example with [[Segment Selector|Segment Selectors]]:

[[File:Segment_Selectors_Screenshot_01.png|800px]]

Bit 0 is the least significant bit, bit 15 is the [[Most Significant Bit]]. Range "bits 3 through 15" ''include'' bit 3 and bit 15 and are 13 bits long, with bit 0 through 1 aka bit 0 and 1 being the [[Requested Priviledge Level|RPL]] and bit 2 (3rd bit) being the [[Table Indicator|TI]].
Additionally, in memory, this is stored [[Little Endian]], so the least significant half of the index + 3 bits for the flags is in the first byte and the most significant half of the index is in the second byte.
Do note that eg. [[NASM]] treats <code>0b</code> as numeric literals, so it'll swap the bytes around - Thus,
<pre>
mov ax, 0000_0000_0000_1000b
mov cs, ax
</pre>
Puts [[Segment Selector]] with [[Requested Priviledge Level|RPL]]=0 into the ''second'' (2, 0b10, 0x2) entry of the ''[[Global Descriptor Table|GDT]]'', with the 1 being the 4th bit aka bit 3 into the [[Code Segment Register|CS register]].
[[Category:X86]]

Intel 64 Architecture

2024-12-19T15:08:32Z

TheCatgirls:

= Architecture =

The Intel 64 Architecture is a 64-bit extension of the 32-bit [[x86]] [[IA-32]] architecture. It was introduced around 2004, reimplementing [[AMD64]], AMD's 64-bit extension.

Both [[AMD64]] and Intel 64 Architecture (from henceforth referred to as I64A; Do not confuse with [[Itanium]], referred to as [[Itanium|IA64]].) are collectively referred to as [[x86_64]], and commonly as [[x86_64|x64]], or [[x86_64|64bit x86]].

I64A introduces a new [[x86 Operating Mode]] to the existing set already present in [[IA32]] referred to as [[IA-32e]], which has two sub-modes, [[IA-32e Compatibility Mode]] and [[IA-32e 64bit Mode]].

= Summary =

I64A is the most common [[x86]] architecture in use today, and as such, we will detail things present in I64A that are also present in other [[x86]] architectures. We will describe average somewhat modern Intel CPU here.

When the system boots up, the [[Intel Managemenet Engine]] (IME) initializes the chipset, then loads the [[Motherboard Firmware]] from its ROM, and jumps to it. The [[Motherboard Firmware]] then initializes the computer, [[Power-On Self Test|POSTs]], and executes its defined [[Firmware Interface]] to load a [[Bootloader]].

The two main [[Firmware Interface|Firmware Interfaces]] are [[Basic Input-Output System|BIOS]] and [[Unified Extensible Firmware Interface|UEFI]]. [[Basic Input-Output System|BIOS]] is older, back from [[Disk Operating System|DOS]] days. [[Unified Extensible Firmware Interface|UEFI]] is newer, and the current preferred standard for most non-legacy applications.

I64A has several [[x86 Operating Mode|operating modes]].
* [[Protected Mode]] (native)
* [[Real-address Mode]] (emulated)
* [[System-management Mode]] (SMM)
* [[Compatibility Mode]] (IA-32e)
* [[64-bit Mode]] (IA-32e)

===== Protected Mode =====
Main article: [[Protected Mode]]
32-bit [[General-Purpose Register|GPR]] set. Instructions default to 32bit (operand size and address size). Addresses consist of a 16-bit [[Segment Selector]] and 32-bit offset.

Protected Mode (henceforth referred to as PM) supports both [[Paging]] and [[Segmentation]].
[[Segmentation]] is ''mandatory'', though it can be configured to be essentially a no-op, a so-called [[Flat Segmentation Model]], eg. if you want to use [[Paging]] only.

Segmentation is configured though a [[Global Descriptor Table]].
===== Real-address Mode =====
Main article: [[Real-address Mode]]
16-bit [[General-Purpose Register|GPR]] set. Essentially just emulates an [[8086]]. Thus, 16-bit addresses with 4-bit [[Segment Registers]] for [[Segment Selector|Segment Selection]]. Do note that ''[[Segment Registers]]'' are different from but interconnected with [[Segmentation]]! [[Segment Selector|Segment Selection]] allows for the existence of several separate address spaces ''only'', it is ''not'' a form of protected memory like [[Protected Mode|PM]]'s [[Segmentation]] - you ''cannot'' configure memory protection (which [[Protected Mode]] gets its name from) controls.
===== System-management Mode =====
Main article: [[System-management Mode]]
It's a part of the APIs the [[Motherboard Firmware]] implementation uses for implementing certain features. Namely, the CPU switches to this mode when it receives a [[System Management Interrupt]], that is, a certain [[Hardware Interrupt]] on the [[System Management Interrupt|SMI]] line (which is kind of like the [[Non-Maskable Interrupt|NMI]] line).

Not to be confused with the [[System Management Module]]. Thanks Intel.
===== Compatibility Mode =====
===== 64-bit Mode =====

[[Category:X86]]

VirtIO

2024-12-19T01:39:26Z

TheCatgirls: Actually, 1.3 is latest, not 1.2

VirtIO is a standard for performant virtualized hardware for use within virtual machines, created and managed by the [https://www.oasis-open.org/committees/tc_home.php?wg_abbrev=virtio OASIS Open Virtual I/O Device TC]. VirtIO supports a variety of devices, such as, but not limited to: block (e.g. hard drive), network card, GPU, etc. Each of these devices have their own specific configuration and features, but all use the same underlying VirtIO queue structure for relaying data and commands to & from the device.

The latest specification, 1.3, is available at https://docs.oasis-open.org/virtio/virtio/v1.3/csd01/virtio-v1.3-csd01.html.

VirtIO provides a common framework for devices to be identified and for communicating between the device implementation and the driver.
Communication for is handled through so-called ''virtqueues''.

Certain implementations extend the features available.

For example, here is the list of virtio-gpu capsets in Mesa, at <code>src/gfxstream/guest/platform/include/virtgpu_gfxstream_protocol.h</code>:
<pre>
#define VIRTGPU_CAPSET_VIRGL 1
#define VIRTGPU_CAPSET_VIRGL2 2
#define VIRTGPU_CAPSET_GFXSTREAM_VULKAN 3
#define VIRTGPU_CAPSET_VENUS 4
#define VIRTGPU_CAPSET_CROSS_DOMAIN 5
#define VIRTGPU_CAPSET_DRM 6
#define VIRTGPU_CAPSET_GFXSTREAM_MAGMA 7
#define VIRTGPU_CAPSET_GFXSTREAM_GLES 8
#define VIRTGPU_CAPSET_GFXSTREAM_COMPOSER 9
</pre>

virtio-gpu can be used to forward various things to Linux hosts, such as native Wayland surfaces, or Linux drm ioctls. Commonly this is used with Linux guests, but there's nothing preventing usage in any other OS running as guest.

=== Device Types ===
{| class="wikitable sortable mw-collapsible"
|+VirtIO Device Types
!Device ID
!Device Name
!Description
|-
|0
|reserved (invalid)
| TODO
|-
|1
|network card
| TODO
|-
|2
|block device
| TODO
|-
|3
|console
| TODO
|-
|4
|entropy source
| TODO
|-
|5
|memory ballooning (traditional)
| TODO
|-
|6
|ioMemory
| TODO
|-
|7
|rpmsg
| TODO
|-
|8
|SCSI host
| TODO
|-
|9
|9P transport
| TODO
|-
|10
|mac80211 wlan
| TODO
|-
|11
|rproc serial
| TODO
|-
|12
|virtio CAIF
| TODO
|-
|13
|memory balloon
| TODO
|-
|16
|GPU device
| TODO
|-
|17
|Timer/Clock device
| TODO
|-
|18
|Input device
| TODO
|-
|19
|Socket device
| TODO
|-
|20
|Crypto device
| TODO
|-
|21
|Signal Distribution Module
| TODO
|-
|22
|pstore device
| TODO
|-
|23
|IOMMU device
| TODO
|-
|24
|Memory device
| TODO
|-
|25
|Audio device
| TODO
|-
|26
|file system device
| TODO
|-
|27
|PMEM device
| TODO
|-
|28
|RPMB device
| TODO
|-
|29
|mac80211 hwsim wireless simulation device
| TODO
|-
|30
|Video encoder device
| TODO
|-
|31
|Video decoder device
| TODO
|-
|32
|SCMI device
| TODO
|-
|33
|NitroSecureModule
| TODO
|-
|34
|I2C adapter
| TODO
|-
|35
|Watchdog
| TODO
|-
|36
|CAN device
| TODO
|-
|38
|Parameter Server
| TODO
|-
|39
|Audio policy device
| TODO
|-
|40
|Bluetooth device
| TODO
|-
|41
|GPIO device
| TODO
|-
|42
|RDMA device
| TODO
|-

|}

=== Device Transports ===
VirtIO supports three different types of device transports: [[PCI|PCI Bus]], [[MMIO]], and [[Channel I/O]]. The PCIe transport is configured via the normal PCIe configuration mechanisms, while the MMIO transport is configured strictly via MMIO reads and writes.

VirtIO

2024-12-19T01:37:44Z

TheCatgirls: s/driver/drm

VirtIO is a standard for performant virtualized hardware for use within virtual machines, created and managed by the [https://www.oasis-open.org/committees/tc_home.php?wg_abbrev=virtio OASIS Open Virtual I/O Device TC]. VirtIO supports a variety of devices, such as, but not limited to: block (e.g. hard drive), network card, GPU, etc. Each of these devices have their own specific configuration and features, but all use the same underlying VirtIO queue structure for relaying data and commands to & from the device.

The latest specification, 1.2, is available at https://docs.oasis-open.org/virtio/virtio/v1.2/csd01/virtio-v1.2-csd01.html.

VirtIO provides a common framework for devices to be identified and for communicating between the device implementation and the driver.
Communication for is handled through so-called ''virtqueues''.

Certain implementations extend the features available.

For example, here is the list of virtio-gpu capsets in Mesa, at <code>src/gfxstream/guest/platform/include/virtgpu_gfxstream_protocol.h</code>:
<pre>
#define VIRTGPU_CAPSET_VIRGL 1
#define VIRTGPU_CAPSET_VIRGL2 2
#define VIRTGPU_CAPSET_GFXSTREAM_VULKAN 3
#define VIRTGPU_CAPSET_VENUS 4
#define VIRTGPU_CAPSET_CROSS_DOMAIN 5
#define VIRTGPU_CAPSET_DRM 6
#define VIRTGPU_CAPSET_GFXSTREAM_MAGMA 7
#define VIRTGPU_CAPSET_GFXSTREAM_GLES 8
#define VIRTGPU_CAPSET_GFXSTREAM_COMPOSER 9
</pre>

virtio-gpu can be used to forward various things to Linux hosts, such as native Wayland surfaces, or Linux drm ioctls. Commonly this is used with Linux guests, but there's nothing preventing usage in any other OS running as guest.

=== Device Types ===
{| class="wikitable sortable mw-collapsible"
|+VirtIO Device Types
!Device ID
!Device Name
!Description
|-
|0
|reserved (invalid)
| TODO
|-
|1
|network card
| TODO
|-
|2
|block device
| TODO
|-
|3
|console
| TODO
|-
|4
|entropy source
| TODO
|-
|5
|memory ballooning (traditional)
| TODO
|-
|6
|ioMemory
| TODO
|-
|7
|rpmsg
| TODO
|-
|8
|SCSI host
| TODO
|-
|9
|9P transport
| TODO
|-
|10
|mac80211 wlan
| TODO
|-
|11
|rproc serial
| TODO
|-
|12
|virtio CAIF
| TODO
|-
|13
|memory balloon
| TODO
|-
|16
|GPU device
| TODO
|-
|17
|Timer/Clock device
| TODO
|-
|18
|Input device
| TODO
|-
|19
|Socket device
| TODO
|-
|20
|Crypto device
| TODO
|-
|21
|Signal Distribution Module
| TODO
|-
|22
|pstore device
| TODO
|-
|23
|IOMMU device
| TODO
|-
|24
|Memory device
| TODO
|-
|25
|Audio device
| TODO
|-
|26
|file system device
| TODO
|-
|27
|PMEM device
| TODO
|-
|28
|RPMB device
| TODO
|-
|29
|mac80211 hwsim wireless simulation device
| TODO
|-
|30
|Video encoder device
| TODO
|-
|31
|Video decoder device
| TODO
|-
|32
|SCMI device
| TODO
|-
|33
|NitroSecureModule
| TODO
|-
|34
|I2C adapter
| TODO
|-
|35
|Watchdog
| TODO
|-
|36
|CAN device
| TODO
|-
|38
|Parameter Server
| TODO
|-
|39
|Audio policy device
| TODO
|-
|40
|Bluetooth device
| TODO
|-
|41
|GPIO device
| TODO
|-
|42
|RDMA device
| TODO
|-

|}

=== Device Transports ===
VirtIO supports three different types of device transports: [[PCI|PCI Bus]], [[MMIO]], and [[Channel I/O]]. The PCIe transport is configured via the normal PCIe configuration mechanisms, while the MMIO transport is configured strictly via MMIO reads and writes.

VirtIO

2024-12-19T01:37:05Z

TheCatgirls: Link to the virtio spec + list the modern virtio-gpu capsets

VirtIO is a standard for performant virtualized hardware for use within virtual machines, created and managed by the [https://www.oasis-open.org/committees/tc_home.php?wg_abbrev=virtio OASIS Open Virtual I/O Device TC]. VirtIO supports a variety of devices, such as, but not limited to: block (e.g. hard drive), network card, GPU, etc. Each of these devices have their own specific configuration and features, but all use the same underlying VirtIO queue structure for relaying data and commands to & from the device.

The latest specification, 1.2, is available at https://docs.oasis-open.org/virtio/virtio/v1.2/csd01/virtio-v1.2-csd01.html.

VirtIO provides a common framework for devices to be identified and for communicating between the device implementation and the driver.
Communication for is handled through so-called ''virtqueues''.

Certain implementations extend the features available.

For example, here is the list of virtio-gpu capsets in Mesa, at <code>src/gfxstream/guest/platform/include/virtgpu_gfxstream_protocol.h</code>:
<pre>
#define VIRTGPU_CAPSET_VIRGL 1
#define VIRTGPU_CAPSET_VIRGL2 2
#define VIRTGPU_CAPSET_GFXSTREAM_VULKAN 3
#define VIRTGPU_CAPSET_VENUS 4
#define VIRTGPU_CAPSET_CROSS_DOMAIN 5
#define VIRTGPU_CAPSET_DRM 6
#define VIRTGPU_CAPSET_GFXSTREAM_MAGMA 7
#define VIRTGPU_CAPSET_GFXSTREAM_GLES 8
#define VIRTGPU_CAPSET_GFXSTREAM_COMPOSER 9
</pre>

virtio-gpu can be used to forward various things to Linux hosts, such as native Wayland surfaces, or Linux driver ioctls. Commonly this is used with Linux guests, but there's nothing preventing usage in any other OS running as guest.

=== Device Types ===
{| class="wikitable sortable mw-collapsible"
|+VirtIO Device Types
!Device ID
!Device Name
!Description
|-
|0
|reserved (invalid)
| TODO
|-
|1
|network card
| TODO
|-
|2
|block device
| TODO
|-
|3
|console
| TODO
|-
|4
|entropy source
| TODO
|-
|5
|memory ballooning (traditional)
| TODO
|-
|6
|ioMemory
| TODO
|-
|7
|rpmsg
| TODO
|-
|8
|SCSI host
| TODO
|-
|9
|9P transport
| TODO
|-
|10
|mac80211 wlan
| TODO
|-
|11
|rproc serial
| TODO
|-
|12
|virtio CAIF
| TODO
|-
|13
|memory balloon
| TODO
|-
|16
|GPU device
| TODO
|-
|17
|Timer/Clock device
| TODO
|-
|18
|Input device
| TODO
|-
|19
|Socket device
| TODO
|-
|20
|Crypto device
| TODO
|-
|21
|Signal Distribution Module
| TODO
|-
|22
|pstore device
| TODO
|-
|23
|IOMMU device
| TODO
|-
|24
|Memory device
| TODO
|-
|25
|Audio device
| TODO
|-
|26
|file system device
| TODO
|-
|27
|PMEM device
| TODO
|-
|28
|RPMB device
| TODO
|-
|29
|mac80211 hwsim wireless simulation device
| TODO
|-
|30
|Video encoder device
| TODO
|-
|31
|Video decoder device
| TODO
|-
|32
|SCMI device
| TODO
|-
|33
|NitroSecureModule
| TODO
|-
|34
|I2C adapter
| TODO
|-
|35
|Watchdog
| TODO
|-
|36
|CAN device
| TODO
|-
|38
|Parameter Server
| TODO
|-
|39
|Audio policy device
| TODO
|-
|40
|Bluetooth device
| TODO
|-
|41
|GPIO device
| TODO
|-
|42
|RDMA device
| TODO
|-

|}

=== Device Transports ===
VirtIO supports three different types of device transports: [[PCI|PCI Bus]], [[MMIO]], and [[Channel I/O]]. The PCIe transport is configured via the normal PCIe configuration mechanisms, while the MMIO transport is configured strictly via MMIO reads and writes.

VirtIO

2024-12-19T01:21:09Z

TheCatgirls: List all device types, TODO fill a description

IA32 Manual Conventions

2024-12-19T00:49:30Z

TheCatgirls: Initial description of some IA32 manual conventions

File:Segment Selectors Screenshot 01.png

2024-12-19T00:45:47Z

TheCatgirls: Screenshot of section 3.4.2 + Figure 3-6 of Volume 3A of the Intel IA32 Software Manual.

== Summary ==
Screenshot of section 3.4.2 + Figure 3-6 of Volume 3A of the Intel IA32 Software Manual.

Intel 64 Architecture

2024-12-18T17:16:04Z

TheCatgirls: IA-32e is an operating mode, not an address mode

= Architecture =

The Intel 64 Architecture is a 64-bit extension of the 32-bit [[x86]] [[IA-32]] architecture. It was introduced around 2004, reimplementing [[AMD64]], AMD's 64-bit extension.

Both [[AMD64]] and Intel 64 Architecture (from henceforth referred to as I64A; Do not confuse with [[Itanium]], referred to as [[Itanium|IA64]].) are collectively referred to as [[x86_64]], and commonly as [[x86_64|x64]], or [[x86_64|64bit x86]].

I64A introduces a new [[x86 Operating Mode]] to the existing set already present in [[IA32]] referred to as [[IA-32e]], which has two sub-modes, [[IA-32e Compatibility Mode]] and [[IA-32e 64bit Mode]].

= Summary =

I64A is the most common [[x86]] architecture in use today, and as such, we will detail things present in I64A that are also present in other [[x86]] architectures. We will describe average somewhat modern Intel CPU here.

When the system boots up, the [[Intel Managemenet Engine]] (IME) initializes the chipset, then loads the [[Motherboard Firmware]] from its ROM, and jumps to it. The [[Motherboard Firmware]] then initializes the computer, [[Power-On Self Test|POSTs]], and executes its defined [[Firmware Interface]] to load a [[Bootloader]].

The two main [[Firmware Interface|Firmware Interfaces]] are [[Basic Input-Output System|BIOS]] and [[Unified Extensible Firmware Interface|UEFI]]. [[Basic Input-Output System|BIOS]] is older, back from [[Disk Operating System|DOS]] days. [[Unified Extensible Firmware Interface|UEFI]] is newer, and the current preferred standard for most non-legacy applications.

I64A has several [[x86 Operating Mode|operating modes]].
* [[Protected Mode]] (native)
* [[Real-address Mode]] (emulated)
* [[System-management Mode]] (SMM)
* [[Compatibility Mode]] (IA-32e)
* [[64-bit Mode]] (IA-32e)

===== Protected Mode =====
Main article: [[Protected Mode]]
32-bit [[General-Purpose Register|GPR]] set. Instructions default to 32bit (operand size and address size). Addresses consist of a 16-bit [[Segment Selector]] and 32-bit offset.

Protected Mode (henceforth referred to as PM) supports both [[Paging]] and [[Segmentation]].
[[Segmentation]] is ''mandatory'', though it can be configured to be essentially a no-op, a so-called [[Flat Segmentation Model]], eg. if you want to use [[Paging]] only.

Segmentation is configured though a [[Global Descriptor Table]].
===== Real-address Mode =====
Main article: [[Real-address Mode]]
16-bit [[General-Purpose Register|GPR]] set. Essentially just emulates an [[8086]]. Thus, 16-bit addresses with 4-bit [[Segment Registers]] for [[Segment Selector|Segment Selection]]. Do note that ''[[Segment Registers]]'' are different from but interconnected with [[Segmentation]]! [[Segment Selector|Segment Selection]] allows for the existence of several separate address spaces ''only'', it is ''not'' a form of protected memory like [[Protected Mode|PM]]'s [[Segmentation]] - you ''cannot'' configure memory protection (which [[Protected Mode]] gets its name from) controls.
===== System-management Mode =====
Main article: [[System-management Mode]]
It's a part of the APIs the [[Motherboard Firmware]] implementation uses for implementing certain features. Namely, the CPU switches to this mode when it receives a [[System Management Interrupt]], that is, a certain [[Hardware Interrupt]] on the [[System Management Interrupt|SMI]] line (which is kind of like the [[Non-Maskable Interrupt|NMI]] line).

Not to be confused with the [[System Management Module]]. Thanks Intel.
===== Compatibility Mode =====
===== 64-bit Mode =====

Intel 64 Architecture

2024-12-18T01:58:56Z

TheCatgirls: Initial version, only general info

= Architecture =

The Intel 64 Architecture is a 64-bit extension of the 32-bit [[x86]] [[IA-32]] architecture. It was introduced around 2004, reimplementing [[AMD64]], AMD's 64-bit extension.

Both [[AMD64]] and Intel 64 Architecture (from henceforth referred to as I64A; Do not confuse with [[Itanium]], referred to as [[Itanium|IA64]].) are collectively referred to as [[x86_64]], and commonly as [[x86_64|x64]], or [[x86_64|64bit x86]].

I64A introduces a new [[x86 Addressing Mode]] to the existing set already present in [[IA32]] referred to as [[IA-32e]], which has two sub-modes, [[IA-32e Compatibility Mode]] and [[IA-32e 64bit Mode]].

= Summary =

I64A is the most common [[x86]] architecture in use today, and as such, we will detail things present in I64A that are also present in other [[x86]] architectures. We will describe average somewhat modern Intel CPU here.

When the system boots up, the [[Intel Managemenet Engine]] (IME) initializes the chipset, then loads the [[Motherboard Firmware]] from its ROM, and jumps to it. The [[Motherboard Firmware]] then initializes the computer, [[Power-On Self Test|POSTs]], and executes its defined [[Firmware Interface]] to load a [[Bootloader]].

The two main [[Firmware Interface|Firmware Interfaces]] are [[Basic Input-Output System|BIOS]] and [[Unified Extensible Firmware Interface|UEFI]]. [[Basic Input-Output System|BIOS]] is older, back from [[Disk Operating System|DOS]] days. [[Unified Extensible Firmware Interface|UEFI]] is newer, and the current preferred standard for most non-legacy applications.

I64A has several operating modes.
* [[Protected Mode]] (native)
* [[Real-address Mode]] (emulated)
* [[System-management Mode]] (SMM)
* [[Compatibility Mode]] (IA-32e)
* [[64-bit Mode]] (IA-32e)

===== Protected Mode =====
Main article: [[Protected Mode]]
32-bit [[General-Purpose Register|GPR]] set. Instructions default to 32bit (operand size and address size). Addresses consist of a 16-bit [[Segment Selector]] and 32-bit offset.

Protected Mode (henceforth referred to as PM) supports both [[Paging]] and [[Segmentation]].
[[Segmentation]] is ''mandatory'', though it can be configured to be essentially a no-op, a so-called [[Flat Segmentation Model]], eg. if you want to use [[Paging]] only.

Segmentation is configured though a [[Global Descriptor Table]].
===== Real-address Mode =====
Main article: [[Real-address Mode]]
16-bit [[General-Purpose Register|GPR]] set. Essentially just emulates an [[8086]]. Thus, 16-bit addresses with 4-bit [[Segment Registers]] for [[Segment Selector|Segment Selection]]. Do note that ''[[Segment Registers]]'' are different from but interconnected with [[Segmentation]]! [[Segment Selector|Segment Selection]] allows for the existence of several separate address spaces ''only'', it is ''not'' a form of protected memory like [[Protected Mode|PM]]'s [[Segmentation]] - you ''cannot'' configure memory protection (which [[Protected Mode]] gets its name from) controls.
===== System-management Mode =====
Main article: [[System-management Mode]]
It's a part of the APIs the [[Motherboard Firmware]] implementation uses for implementing certain features. Namely, the CPU switches to this mode when it receives a [[System Management Interrupt]], that is, a certain [[Hardware Interrupt]] on the [[System Management Interrupt|SMI]] line (which is kind of like the [[Non-Maskable Interrupt|NMI]] line).

Not to be confused with the [[System Management Module]]. Thanks Intel.
===== Compatibility Mode =====
===== 64-bit Mode =====